Zhiyuan He and Test Scheduling - Free people check

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Thermal Issues in Testing of Advanced Systems on Chip - Nima Aghaee...

books.google.ca

Zhiyuan He, Zebo Peng, and P Eles. POWER CONSTRAINED AND DEFECTPROBABILITY DRIVEN SOC TEST SCHEDULING WITH TEST SET PARTITIONING ...

Temperature Aware and Defect-probability Driven Test Scheduling for...

books.google.de

Temperature Aware and Defect-probability Driven Test Scheduling for System-on-chip. Front Cover. Zhiyuan He. Department of Computer and Information ...

Zhiyuan He - DiVA

liu.diva-portal.org

Temperature Aware and Defect-Probability Driven Test Scheduling for System-on-Chip. Zhiyuan He. Temperature Aware and. Defect-Probability Driven.

Zhiyuan He , Zebo Peng , Petru Eles, Power ACM Digital Library

dl.acm.org

Zhiyuan He , Gert Jervan , Zebo Peng , Petru Eles, Hybrid BIST Test Scheduling Based on Defect Probabilities, Proceedings of the 13th Asian ...

Thermal-Aware SoC Test Scheduling with Test Set Partitioning and...

www.diva-portal.org

Thermal-Aware SoC Test Scheduling with Test Set Partitioning and ... Zhiyuan He, Zebo Peng, Petru ... Thermal-Aware SoC Test Scheduling with Test Set Partitioning …

CiteSeerX — Thermal-aware SoC test scheduling with test set...

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Thermal-aware SoC test scheduling with test set partitioning and ... {Zhiyuan He and Zebo Peng and Petru ... {Thermal-aware SoC test scheduling with test set ...

CORE

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Thermal-aware SoC test scheduling with test set partitioning and interleaving . By Zhiyuan He, Zebo Peng, ...

All web results to the name "Zhiyuan He"

Sökresultat - IDA

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Test Scheduling with Test Set Partitioning Zhiyuan He, Zebo Peng, and Petru Eles Embedded Systems Laboratory (ESLAB) Linköping University, Sweden ...

A heuristic for thermal-safe SoC test scheduling

www.infona.pl

High temperature has become a technological barrier to the testing of high performance systems-on-chip, especially when deep submicron technologies are...