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KABUSHIKI KAISHA TOSHIBA, Tokyo, JP
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Method for manufacturing an insulating trench in a substrate for...
www.freepatentsonline.com
For manufacturing an insulation trench in a SOI substrate wherein logic components and high-voltage power components are integrated, a trench extending down...
Miscellaneous
US A - Method for manufacturing an insulating trench in an SOI...
patents.google.com
A method for producing an insulating trench in an SOI substrate having integrated logic elements and high-voltage power components is provided. A trench...
DE D Mos-performance field effect transistor and process...
patents.google.com
Hirohito Tanabe, Yu Ohata, Kazuaki Suzuki, Toshiba Shinkoyasu Apato Miwa, Yoshihito Nakayama: Applicant: Toshiba Kawasaki Kk: Export Citation: BiBTeX, EndNote, RefMan:
Yu Ohata (@blackyu) Instagram top photos, videos
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Yu Ohata blackyu. website: http://yuohata.tumblr.com; bio: ❝Japanese interior designer from China shenzhen❞ 日本人内装设计师在深圳; number of photos:
Japanese Restaurant Nare Sushi Debuts in Manhattan’s Midtown East |...
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Nare Sushi, a new Japanese restaurant located in the heart of Manhattan’s Midtown East neighborhood, officially opened to the public Monday following a soft...
EP A2 - Multi-output vertical type power semiconductor device...
patents.google.com
Portland, US; YU OHATA et al.: "Dielectrically isolated intelligent power switch".
EP A3 - Power mosfet Google Patents
patents.google.com
... EP-A , EP A3, EP A3, EP , EP Inventeurs, Hirohito Tanabe, Yu Ohata, Yukiharu Miwa, Tsuyoshi Kuramoto.
US A - Power semiconductor device Google Patents
patents.google.com
Isolated Intelligent Power Switch, Yu Ohata et al., Toshiba Semiconductor,
Division ...
US A - Dielectrics dividing wafer Google Patents
patents.google.com
A dielectrics dividing wafer is disclosed in which embedded dielectric films are provided in the interior of the wafer in a predetermined pattern...
US A - Semiconductor substrate structure for producing two...
patents.google.com
A semiconductor circuit structure including a semiconductor substrate portion and at least one region provided on one main surface thereof insulatedly...
EP A1 - Power MOS FET and method of manufacturing the same...
patents.google.com
Inventeurs, Hirohito Tanabe, Yu Ohata, Kazuaki Suzuki, Yukiharu 207 Toshiba Shinkoyasu Apato Miwa, Yoshihito Nakayama. Déposant, Kabushiki Kaisha ...
EP A1 - Verfahren zur Herstellung eines Grabens in einem...
patents.google.com
... von den Logikbauelementen erforderlich. [0004]. Es ist bekannt (siehe zum Beispiel Yu Ohata et al, IEEE CICC, S bis 446; A. Nakagawa et al. ISPS
US A - Semiconductor device whose output characteristic can be...
patents.google.com
A semiconductor device includes a resistor network having a plurality of trimming polysilicon resistors. The polysilicon resistors have the same width...
DE T Substrate structure for manufacturing a semiconductor...
patents.google.com
... DE T2, DE-T , DE , DE T2, DE T2, DE Inventors, Koichi Kitahara, Yu Ohata, Tsuyoshi Kuramoto.
DE D1 - Halbleiterbauelement, dessen Ausgangscharakteristiken...
patents.google.com
... DE D1, DE-D , DE , DE D1, DE D1, DE Inventors, Yu Ohata, Yosuke Takagi, Koichi Kitahara.
DE T2 - Halbleiterbauelement, dessen Ausgangscharakteristiken...
patents.google.com
... DE T2, DE-T , DE , DE T2, DE T2, DE Inventors, Yu Ohata, Yosuke Takagi, Koichi Kitahara.
EP B1 - Power mos fet and method of manufacturing the same...
patents.google.com
Inventors, Hirohito Tanabe, Yu Ohata, Kazuaki Suzuki, Yukiharu 207 Toshiba Shinkoyasu Apato Miwa, Yoshihito Nakayama. Applicant, Kabushiki Kaisha ...
US A - Method for manufacturing a trench in a substrate for use...
patents.google.com
A method for manufacturing a trench in a substrate that has at least a first silicon layer, an insulating layer and a second silicon layer is disclosed....
DE A A process for the preparation of an adjacent trench a...
patents.google.com
... direct wafer bon ding (DWB) or silicon direct bonding (SDB) method, which is known for example from Yu Ohata et al, IEEE 1987, pages , is produced.
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