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LinkedIn: Yavar Safaei Mehrabani | LinkedIn
View Yavar’s full profile A Novel High-Performance and Reliable Multi-Threshold CNFET Full Adder Cell Design A NOVEL HIGH-SPEED, LOW-POWER CNTFET-BASED INEXACT FULL ADDER CELL FOR IMAGE PROCESSING APPLICATION OF MOTION DETECTOR.
Dr. Yavar Safaei Mehrabani (@yavar_safaei)`s Instagram Profile | Picgra
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List of (1) Instagram media taken by Dr. Yavar Safaei Mehrabani (@yavar_safaei) | Bio: ▫دکتری تخصصی کامپیوتر ▫متخصص در زمینه اینترنت اشیاء ▫متخصص در ...
Books & Literature
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von Khademzadeh, Zahra Zareei Yavar Safaei Mehrabani Ahmad. International Journal of High Performance Systems Architecture. Jan 31, 2014, Vol. 4 Issue
authors:"Yavar Safaei Mehrabani" - Search | Paperity
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Yavar Safaei Mehrabani - researchr alias
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Publications by 'Yavar Safaei Mehrabani'. Publications; Advised. No publications in this list. About · Contact · Credits · Help · Web Service API · Blog · FAQ ...
CiteSeerX — Efficient Power-Delay Product Modulo 2 � �1 Adder Design
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BibTeX @MISC{Mehrabani_efficientpower-delay, author = {Yavar Safaei Mehrabani and Mehdi Hosseinzadeh}, title = {Efficient Power-Delay Product Modulo 2 1 Adder ...
A high-speed and high-performance full adder cell based on 32-nm...
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A high-speed and high-performance full adder cell. based on 32-nm CNFET technology for low voltages. Yavar Safaei Mehrabani*. Young Researchers and ...
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761, --, 0, Yavar Safaei Mehrabani, Mohammad Eshghi. Erratum to: A Symmetric, Multi-Threshold, High-Speed and Efficient-Energy 1-Bit Full Adder Cell Design Using CNFET Technology. 763, --, 778, R. Rakkiyappan, R. Sivasamy, Xiaodi Li. Synchronization of Identical and Nonidentical Memristor-based Chaotic Systems ...
Scientific Publications
dblp: Yavar Safaei Mehrabani
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List of computer science publications by Yavar Safaei Mehrabani
CNT
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Mehrabani Yavar Safaei, Eshghi Mohammad: Noise and Process Variation Tolerant, Low-Power, High-Speed, and Low-Energy Full Adders in CNFET Technology. IEEE Trans on VLSI Systems, Vol. 24, no. 11, 2016, pp – DOI TVLSI Liu Yang, Wang Sheng, Peng Lian-Mao: Toward ...
dblp: Circuits, Systems, and Signal Processing, Volume 34
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Bibliographic content of Circuits, Systems, and Signal Processing, Volume 34
dblp: Mohammad Hossein Shafiabadi
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List of computer science publications by Mohammad Hossein Shafiabadi
Miscellaneous
Yavar Safaei Mehrabani | LinkedIn
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Yavar Safaei Mehrabani
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Erratum to: A Symmetric, Multi-Threshold, High-Speed and Efficient-Energy 1-Bit Full Adder Cell Design Using CNFET Technology · Yavar Safaei Mehrabani ...
TDGS - "PDP"
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Bibliography Refine on click | Report | Share. More than 125 records ... Yavar Safaei Mehrabani, Mohammad Eshghi. Journal of Circuits ...
International Journal of High Performance Systems Architecture...
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Yavar Safaei Mehrabani; Zahra Zareei; Ahmad Khademzadeh DOI: IJHPSA , Design and VLSI implementation of power efficient ...
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Yavar Safaei Mehrabani, Mehdi Hosseinzadeh. Abstract: As embedded and portable systems were emerged power consumption of circuits had been major ...
A Low-Power and Low-Energy 1-Bit Full Adder Cell Using 32nm CNFET...
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Author(s): Meysam Mohammadi Department of Computer Engineering, Ayatollah Amoli Branch, Islamic Azad University, Amol, Iran Yavar Safaei Mehrabani ...
A Low-Power and Low-Energy 1-Bit Full Adder Cell Using 32nm CNFET...
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دانلود و دریافت مقاله A Low-Power and Low-Energy 1-Bit Full Adder Cell Using 32nm CNFET Technology Node
@article{3067, author = "Nasibeh Rahmani and Yavar ...
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@article{3067, author = "Nasibeh Rahmani and Yavar Safaei Mehrabani", abstract = "Using both Capacitive Threshold Logic (CTL) and Transmission Gate ...
A high-speed and high-performance full adder cell based on 32-nm...
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A high-speed and high-performance full adder cell based on 32-nm...
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Author: YAVAR SAFAEI MEHRABANI1 ; ZAREEI, Zahra2 ; KHADEMZADEH, Ahmad3 [1] Young Researchers and Elites Club, Science and Research Branch, ...
Efficient Power-Delay Product Modulo 2n+1 Adder Design | Zenodo
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Efficient Power-Delay Product Modulo 2n+1 Adder Design. Yavar Safaei Mehrabani; Mehdi Hosseinzadeh. As embedded and portable systems were emerged power consumption of circuits had been major challenge. On the other hand latency as determines frequency of circuits is also vital task. Therefore ...
TDGS - "IJHPSA"
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Yavar Safaei Mehrabani, Reza Faghih Mirzaee, Mohammad Eshghi. IJHPSA, 5(4) : , Fetch ...
Erratum to: A Symmetric, Multi-Threshold, High-Speed and...
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Erratum to: A Symmetric, Multi-Threshold, High-Speed and Efficient-Energy 1-Bit Full Adder Cell Design Using CNFET Technology. Yavar Safaei Mehrabani, Mohammad Eshghi · Details · Contributors · Fields of science · Bibliography · Quotations · Similar · Collections ...
Publications | World Academy of Science, Engineering and Technology
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Publications, World Academy of Science, Engineering and Technology
Design of an ASIP Processor for Mathematic Functions |...
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Yavar Safaei Mehrabani, Mohammad Eshghi “Desing of an ASIP processor for MD5 hash algorithm” 20th Telecommunications forum TELFOR Serbia, ...
IKCESTwww.ikcest.org/paper_list.htm?pid=10&pageNum=14
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Yavar Safaei Mehrabani; Mohammad Eshghi;. process variation; Carbon nanotube field-effect transistor (CNFET); full adder; low-energy; noise;. Temperature ...
Efficient Power-Delay Product Modulo 2n+1 Adder Designpublications.waset.org › ...
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Authors: Yavar Safaei Mehrabani, Mehdi Hosseinzadeh. Abstract: As embedded and portable systems were emerged power consumption of circuits had been ...
OUCI
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Yavar Safaei Mehrabani, Mehdi Bagherizadeh, Mohammad Hossein Shafiabadi, ... Roghayeh Ataie, Azadeh Alsadat Emrani Zarandi, Yavar Safaei Mehrabani.
TDGS - "Ahmad Khademzadeh"
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... and high-performance full adder cell based on 32-nm CNFET technology for low voltages · Yavar Safaei Mehrabani, Zahra Zareei, Ahmad Khademzadeh.
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