(1 - 13 from 14
)
Evatronix Adds the SDLL NAND Flash PHY IP to Its Memory ...
smtnet.com
Mar 23, — ... are confirming our focus on PHY IP announced last month through the release of the USB HSIC PHY,” said Wojciech Sakowski, Evatronix CEO. › news
Evatronix Enhances its USB Portfolio with High Speed Inter ...
www.electronicspecifier.com
Feb 15, — ... the USBHSIC-PHY is the next step in the Evatronix strategy of delivering complete USB solutions,” said Wojciech Sakowski, Evatronix CEO. › news › analysis
Evatronix Releases USB 2.0 High Speed PHY to Complement its USB...
www.eejournal.com
Jun 27, · ... USB 2.0 PHY we passed next significant milestone in our strategy to offer complete front-to-back IP solutions,” said Wojciech Sakowski, Evatronix CEO.
Evatronix Facilitates Chip-to-chip USB Connectivity with its High...
www.eejournal.com
Direct chip-to-chip interconnect allows significant power and silicon area savings while retaining all performance features of the USB 2.0 standard.
sorted by relevance / date