Network Profiles
LinkedIn: Sudeb Dasgupta – Associate Professor, VLSI Design, Low ...
Sehen Sie sich das Profil von Sudeb Dasgupta auf LinkedIn an, dem weltweit größten beruflichen Netzwerk. 2 Jobs sind im Profil von Sudeb Dasgupta aufgelistet. Sehen Sie sich auf LinkedIn das vollständige Profil an. Erfahren Sie mehr über die Kontakte von Sudeb Dasgupta und über Jobs bei ähnlichen Unternehmen.
LinkedIn: Sudeb Dasgupta – Professor – Indian Institute of ...
Sehen Sie sich das Profil von Sudeb Dasgupta auf LinkedIn an, dem weltweit größten beruflichen Netzwerk. 1 Job ist im Profil von Sudeb Dasgupta aufgelistet. Sehen Sie sich auf LinkedIn das vollständige Profil an. Erfahren Sie mehr über die Kontakte von Sudeb Dasgupta und über Jobs bei ähnlichen Unternehmen.
LinkedIn: Sudeb Dasgupta - Associate Professor, VLSI Design, Low ...
View Sudeb Dasgupta’s profile on LinkedIn, the world's largest professional community. Sudeb has 2 jobs listed on their profile. See the complete profile on LinkedIn and discover Sudeb’s connections and jobs at similar companies.
Business Profiles
Researchgate: Sudeb Dasgupta
Roorkee, Uttarakhand, India
Sudeb Dasgupta - Teaching and Research - IIT-Roorkee
www.siliconindia.com
Sudeb Dasgupta 's profile on SiliconIndia. Join SiliconIndia and get connected with Sudeb Dasgupta and others. SiliconIndia keeps you updated with the latest...
Books & Literature
Spacer Engineered FinFET Architectures, High-Performance ...www.booktopia.com.au › ebooks › prod
www.booktopia.com.au
Booktopia has Spacer Engineered FinFET Architectures, High-Performance Digital Circuit Applications by Sudeb Dasgupta. Buy a discounted PDF of Spacer ...
adlibris.com: Spacer Engineered FinFET Architectures - Sudeb Dasgupta ...www.adlibris.com › bok › spacer-engineered-finfet...
Pris: kr. inbunden, Skickas inom 4-6 vardagar. Köp boken Spacer Engineered FinFET Architectures av Sudeb Dasgupta (ISBN ) hos ...
Sudeb Dasgupta (Author of Spacer Engineered FinFET Architectures)
www.goodreads.com
Sudeb Dasgupta is the author of Spacer Engineered FinFET Architectures (5.00 avg rating, 1 rating, 0 reviews), Spacer Engineered Finfet Architectures (0....
Radiation hard circuit design: flip-flop and IET Digital Librarydigital-library.theiet.org › content › books
digital-library.theiet.org
Author(s): Gaurav Kaushal 1 ; Surendra S. Rathod 2 ; Ch Naga Raghuram 3 ; Sudeb Dasgupta 4. View affiliations. Affiliations: 1: Department of Electronics and ...
Related Documents
Quantum Mechanical Analytical Drain Current Modeling and Simulation...
researchr.org
Balwinder Raj, Ashok K. Saxena, Sudeb Dasgupta. Quantum Mechanical Analytical Drain Current Modeling and Simulation for Double Gate FinFET Device ...
[ ] Efficient Implementation of LMS Adaptive Filter ...arxiv.org › eess
arxiv.org
Authors:Bhavya Vasudeva, Puneesh Deora, Pyari Mohan Pradhan, Sudeb Dasgupta. (Submitted on 14 Oct (v1), last revised 19 Feb (this version, v2)).
EBSCOhost | | Radiation Effects in MOS-based Devices and...
web.a.ebscohost.com
Surendra Singh Rathod, A. K. Saxena and Sudeb Dasgupta. Departments of Electronics and Computer Engineering, Indian Institute of Technology, Roorkee, ...
k Spacers - researchr publication authors
researchr.org
Sudeb Dasgupta. This author has not been identified. Look up 'Sudeb Dasgupta' in Google · About · Contact · Credits · Help · Web Service API · Blog · FAQ ...
Scientific Publications
dblp: Journal of Computers, Volume 3
dblp.uni-trier.de
Bibliographic content of Journal of Computers, Volume 3
FIS - Forschungsinformationssystem der TU Dresden
forschungsinfo.tu-dresden.de
Bereich Ingenieurwissenschaften - Fakultät Elektrotechnik und Informationstechnik. Herr Prof. Dr. Sudeb Dasgupta. Heimatinstitut/Einrichtung.
DBLP - Sudeb Dasgupta
dblp.cloudmining.net
Sudeb Dasgupta. Found 27 results. sorted by: number of citations Naushad Alam, Bulusu Anand
The impact of process (3): Surendra S. Rathod, Ashok K. Saxena
Analysis of double (4):
Publications
bol.com: Sudeb Dasgupta artikelen kopen? Alle artikelen online - bol.comwww.bol.com › sudeb-dasgupta
Op zoek naar artikelen van Sudeb Dasgupta? Artikelen van Sudeb Dasgupta koop je eenvoudig online bij bol.com ✓ Snel in huis ✓ Veelal gratis verzonden.
JLPEA | Free Full-Text | Design and Analysis of Double-Gate MOSFETs...
www.mdpi.com
Ramesh Vaddi 1,* , Rajendra P. Agarwal 2 , Sudeb Dasgupta 3 and Tony T. Kim 1. + Authors' affiliations. 1 VIRTUS, School of Electrical and ...
Oalib search
www.oalib.com
Ramesh Vaddi,Rajendra P. Agarwal,Sudeb Dasgupta,Tony T. Kim Journal of Low Power Electronics and Applications , 2011, DOI: jlpea Abstract: Recently, double-gate MOSFETs (DGMOSFETs) have been shown to be more optimal for ultra-low power circuit design due to the improved subthreshold slope and the reduced leakage current compared ...
Analog Performance Analysis of Dual-k Spacer Based Underlap FinFET |...
link.springer.com
In this paper we have analysed the analog performance of conventional as well as dual-k spacer based underlap FinFET. Dual-k spacer in underlap FinFET is used...
Miscellaneous
Sudeb Dasgupta - Professor - Indian Institute of ...
www.linkedin.com
View Sudeb Dasgupta’s profile on LinkedIn, the world's largest professional community. Sudeb has 1 job listed on their profile. See the complete profile on LinkedIn and discover Sudeb’s ...
Ramesh Vaddi - Google Scholar Citations
scholar.google.co.in
h-index, 4, 4. i10-index, 3, Co-authorsView all… Sudeb Dasgupta,; Tae-Hyoung KIM, Tony,; Huichu Liu · Title, Cited by ...
SUDEB DASGUPTA | DIN : | Director Details ...www.instafinancials.com › director › sudeb-dasgupta
www.instafinancials.com
SUDEB DASGUPTA bearing DIN: is holding active directorship in 1 Company. The total paid up capital of all companies where SUDEB DASGUPTA ...
Sudeb Dasgupta
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Latest info on Sudeb Dasgupta. Reviews, comments, videos, discussion and posts of Sudeb Dasgupta. Be a part of TheReviewBay community to add and share reviews.
Sudeb Dasgupta | IIT Roorkee | Indiabiography.omicsonline.org › iit-roorkee › sudeb-dasgupta
biography.omicsonline.org
Sudeb Dasgupta. Electronics and Communication Engineering IIT Roorkee India. Biography. He is working as a Professor in the IIT Roorke in the Department of ...
Sudeb Dasgupta's Profile - IIT BHU Global Alumni Associationconnect.iitbhuglobal.org › sudeb-dasgupta
connect.iitbhuglobal.org
Dr. Sudeb Dasgupta. Ph.D , ECE. Please register to access content on this page. Click here to Register. If you are already a member, please login.
Sudeb Dasgupta | IIT Roorkee - Academia.edu
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Prabook
prabook.com
Sudeb Dasgupta, Indian electronics engineer, educator. Achievements include design of metal–oxide–semiconductor based device known as Parrall Connected Hetero Material Gate (PCHEM) Double Gate Metal–oxide–semiconductor field-effect transistor for their use as a low power substitute to conventional MOSFETs.
4. Saket Gupta, Sparsh Mittal and Sudeb Dasgupta ...
home.eng.iastate.edu
Graduate Student (PhD). Electrical and Computer Engineering. Iowa State University, Ames, IA , USA. Email: sparsh AT iastate.edu.
Sudeb Dasgupta (Indian Institute of Technology Roorkee ...
www.getcited.org
Electronics Engineering; Solid State Electronics; Microelectronics; VLSI' nanoelectroncs; nanoscale MOSFET modelling; gate leakage current ...
Device and Circuit Co-Design Robustness Studies in the ...
www.academia.edu
Sudeb Dasgupta IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 3, MARCH Device and Circuit Co-Design Robustness Studies in the Subthreshold Logic for Ultralow-Power Applications for 32 nm CMOS Ramesh Vaddi, S. Dasgupta, and R. P. Agarwal, Senior Member, IEEE Abstract—Digital circuits operating in a subthreshold region these ...
(PDF) Two-dimensional numerical modeling of lightly doped nano-scale...
www.academia.edu
Sudeb Dasgupta. Download with Google Download with Facebook or download with email. Two-dimensional numerical modeling of lightly doped nano-scale double-gate MOSFET. Download. Two-dimensional numerical modeling of lightly doped nano-scale double-gate MOSFET. Sudeb Dasgupta.
12 bit Digital to Analog Converter | EEWeb Community
www.eeweb.com
Designed a 12 bit CMOS D/A converter employing a segmented hybrid architecture consisting of two thermometer coded current steering segments of 4 bits each & a...
Combinational Logic Design-II video lecture by Prof Prof. Sudeb...
freevideolectures.com
Combinational Logic Design-II tutorial of CMOS Digital VLSI Design course by Prof Prof. Sudeb Dasgupta of IIT Roorkee. You can download the course for FREE !
DISCOVER DEEPANJAN
deep-datta.tripod.com
Mentor: Dr. Sudeb Dasgupta (I.I.T. Roorkee). Duration: February August Organizational Activities: 1)Established IEEE Student ...
Journal of Low Power Electronics and Applications - ISSN:
journaldatabase.info
Academic Journals Database is a universal index of periodical literature covering basic research from all fields of knowledge, and is particularly strong in...
Encore -- Progress in VLSI design and test [electronic resource ...
encore.library.cofc.edu
... Spacer Based Underlap FinFET / Ashutosh Nandi, Ashok K. Saxena and Sudeb Dasgupta -- Implementation of Gating Technique with Modified Scan Flip-Flop ...
SMVDU organizes expert lecture on Nano-electronics, VLSI
www.dailyexcelsior.com
Daily Excelsior is the Largest Circulated Daily of Jammu & Kashmir covering the Latest Jk news of Jammu and Kashmir , India and the World
Sparsh Mittal - Publications List
publicationslist.org
Saket Gupta, Sparsh Mittal, Sudeb Dasgupta (2008) Guaranteed QoS with MIMO systems for Scalable Low Motion Video Streaming over Scarce Resource ...
XPLORE Library Catalog
xplore.xavier.edu
... Spacer Based Underlap FinFET / Ashutosh Nandi, Ashok K. Saxena and Sudeb Dasgupta -- Implementation of Gating Technique with Modified Scan Flip-Flop ...
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