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LinkedIn: SHOJI SHUKURI - LinkedIn
SHOJI SHUKURIさんのプロフィールをチェックしましょう。LinkedInは、SHOJI SHUKURIさんのような方が活動する世界最大のプロフェッショナルネットワークです。今すぐ ...
Interests
Shoji Shukuri - Patents
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Recent bibliographic sampling of Shoji Shukuri patents listed/published in the public domain by the USPTO (USPTO Patent Application #,Title): ...
Shoji Shukuri, Inventor, Koganei, JP
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Shoji Shukuri's Inventor profile, Tokyo, JP185 patents/applications from Apr 15, to Jul 03, 2018, forward patent citations, SPECIFIC USES OR...
Renesas Electronics Corporation patent inventors (2015)stks.freshpatents.com › Renesas-Electronics-Corporation-inventors-nm2
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Shoji Shukuri · Shorin Kyo · Shorin Kyo · Shorin Kyo · Shoutarou Kitamura · Shuichi Kudo · Shuji Satoh · Shunichi Abe · Shunichi Kaeriyama · Shunichi Narumi.
Renesas Electronics Corporation patent inventors (2017)
stks.freshpatents.com
Shoichi Kamimura · Shoji Hashizume · Shoji Muramatsu · Shoji Nakashima · Shoji Shukuri · Shorin Kyo · Shoutarou Kitamura · Shuji Ikeda · Shunichi Kaeriyama.
Business Profiles
patentbuddy: Shoji Shukuri
GENUSION, INC., Koganei, JP
Education
IEICE SEARCH SYSTEM
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Edward W. SCHECKLER Taro OGAWA Shoji SHUKURI Eiji TAKEDA : Summary | Full Text:PDF (766.7KB) >
IEICE Trans - CMOS Process Compatible ie-Flash (Inverse Gate...
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CMOS Process Compatible ie-Flash (Inverse Gate Electrode Flash) Technology for System-on-a Chip Shoji SHUKURI Kazumasa YANAGISAWA Koichiro ...
IEICE SEARCH SYSTEMsearch.ieice.org › bin
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Material Representations and Algorithms for Nanometer Lithography Simulation Edward W. SCHECKLER Taro OGAWA Shoji SHUKURI Eiji TAKEDA.
Books & Literature
BiCMOS Technology and Applications - Google Books
books.google.es
7] Yoji Nishio, Fumio Murabayashi, Shoichi Kotoku, Atsuo Watanabe, Shoji Shukuri, Katsuhiro Shimohigashi, "A BiCMOS Logic Gate with Positive Feedback", ...
DRAM Circuit Design: Fundamental and High-Speed Topics - Brent Keeth,...
books.google.es
[13] Kazuhiko Sagara, Tokuo Kure, Shoji Shukuri, Jiro Yugami, Norio Hasegawa, Hidekazu Goto, and Hisaomi Yamashita, "Recessed memory array technology ...
Frontiers of Materials Research: Electronic and Optical ...
books.google.es
Shoji Shukuri. Yasuo Nada. Masao Tamura. Hiroo Masuda and Tohru Ishitanni: Extended Abstracts of 16th Conf. Solid State Devices and Materials (Jpn. Soc.
Proceedings of the Symposium on Reduced Temperature ...
books.google.es
MOS DEVICE APPLICATION OF FOCUSED ION BEAM DOPING Yasuo Wada, Shoji Shukuri, Masao Tamura, Hiroo Masuda and Toru Ishitani Central Research ...
Related Documents
Semiconductor device - Hitachi, Ltd.
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In manufacturing a semiconductor memory by using conventional gain cells, it is difficult to integrate them similarly to 1T1C cells of a DRAM if mask alignment...
CiteSeerX — Trends of Semiconductor Technology for Total System...
citeseerx.ist.psu.edu
@MISC{Hotta_trendsof, author = {Masao Hotta and Shoji Shukuri and Koichi Nagasawa}, title = {Trends of Semiconductor Technology for Total System Solutions}, year ...
Semiconductor memory device - Semiconductor Energy Laboratory Co.,...
www.freepatentsonline.com
To increase a storage capacity of a memory module per unit area, and to provide a memory module with low power consumption, a transistor formed using an oxide...
Scientific Publications
Patents Assigned to Genusion Inc. - Justia Patents Search
patents.justia.com
Filed: December 14, Date of Patent: November 25, Assignee: Genusion, Inc. Inventors: Natsuo Ajika, Shoji Shukuri, Satoshi Shimizu, Taku Ogura ...
Dynamic disordering process in Si during high dose rate B+ ion beam...
www.sciencedirect.com
The dynamic disordering process in Si during high dose rate focused Bf ion beam (beam diameter 1-2 pm, current density A/cm*) implantation has been ...
Publications
Digital Design | SpringerLink
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The development of advanced BiCMOS processes has given the design engineer new flexibility with regards to basic digital design techniques. Conventional TTL,...
Airiti Library華藝線上圖書館
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[11] Shoji Shukuri, Natsuo Ajika, Masaaki Mihara, Kazuo Kobayashi, ...
Airiti Library華藝線上圖書館_應用矽化鍺通道與低跨越能障穿隧 ...www.airitilibrary.com › Publication › alDetailedMesh
www.airitilibrary.com
[1] Deleep R. Nair, Nihar R. Mohapatra, Souvik Mahapatra, Shoji Shukuri, and Jeff D. Bude, “Effect of P/E Cycling on Drain Disturb in Flash EEPROMs Under ...
Miscellaneous
SHOJI SHUKURI | LinkedIn
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View SHOJI SHUKURI's professional profile on LinkedIn. LinkedIn is the world's largest business network, helping professionals like SHOJI SHUKURI discover inside
US A - Single poly non-volatile memory having a PMOS write path...
patents.google.com
A single-poly, floating gate memory cell includes a PMOS write and an NMOS read path. The memory cell's write path includes a PMOS half-transistor...
US A1 - Semiconductor device and fabricating method thereof...
patents.google.com
A semiconductor device including a substrate, a gate dielectric layer, a gate, a pair of source/drain regions and a stressed layer is disclosed. The gate...
US A - Integrated circuit memory devices having nonvolatile...
patents.google.com
Integrated circuit memory devices include a gate oxide insulating layer on a surface of a semiconductor substrate containing a bulk region of first...
Doc.: IEEE wng Submission Nov Ted Rappaport, WNCG, Univ of...
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... Rappaport, WNCG, Univ of TexasSlide 5 Wireless Technology and Semiconductor ROADMAP Source: 1. Hotta, Imasao, Shoji Shukuri, and Koichi Nagasawa.
Shoji Shukuri_爱学术
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摘要：Provided is a multiple glass shoji screen that can maintain the position of butyl serving as a sealing member and achieve a seal between a spacer ...
US B2 - Circuit for matching semiconductor device behavior...
patents.google.com
A selection circuit. The selection circuit comprises a logic circuit, an array of sub-circuits and a switching circuit electrically coupled to each...
US A - NROM fabrication method with a periphery portion...
patents.google.com
Citações Não Provenientes de Patentes. Referência; 1: ... Shoji Shukuri: Semiconductor integrated circuit device and a method of manufacturing the same
US A - Complementary mos logic circuit Google Patents
patents.google.com
Patents Publication number: US A: Publication type: Grant ... Shoji Shukuri: Semiconductor integrated circuit and nonvolatile memory element: US *
Shoji Shukuri, Koganei JP - Patent applications
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Patent application number, Description, Published , SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND A METHOD OF ...
US B2 - Electronic control device - Google Patents
patents.google.com
US A1 * Shoji Shukuri Semiconductor device with improved latch arrangement. Family To Family Citations. JP B2 ...
US A1 - Nonvolatile Semiconductor Memory ...www.google.ch › patents
patents.google.com
Download PDF Find Prior Art Similar. Inventor: Taku Ogura: Natsuo Ajika: Shoji Shukuri: Satoshi Shimizu: Yoshiki Kawajiri: Masaaki Mihara; Current Assignee.
US A - Method of manufacturing a semiconductor device having...
patents.google.com
US *, 7 Aug 2003, 19 Feb 2004, Shoji Shukuri, Semiconductor Dec 2007, Shoji Shukuri, Semiconductor integrated circuit device having ...
Shoji Shukuri, Hyogo JP - Patent applications
www.patentsencyclopedia.com
Patent application number Description Published; : Nonvolatile Semiconductor Storage Device and Method for Writing Therein - A hot electron (BBHE) is
US A - Semiconductor device having dual gate and method of...
patents.google.com
The invention comprises a method of forming a semiconductor device is provided where a first gate insulator layer 26 is formed on an outer surface of...
US A - Method for manufacturing thick gate oxide device...
patents.google.com
A method for forming devices having a thick gate oxide. The method comprises the steps of providing a substrate having different device areas already...
US A - Semiconductor device comprising an analogue element and...
patents.google.com
A semiconductor device, comprises a semiconductor substrate, a digital element part as a pair of MOS transistors formed on the semiconductor substrate;...
Nonvolatile Semiconductor Memory - Patent application
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Design of Nonvolatile Semiconductor Memory Utilizing the Above Described Method for Programming ... Patent applications by Shoji Shukuri, Hyogo JP.
US B2 - Different thickness oxide silicon nanowire field effect...
patents.google.com
US A1 * Shoji Shukuri Semiconductor integrated circuit device having deposited layer for gate insulation.
US A - Method of controlling non-volatile ferroelectric memory...
patents.google.com
A potential level is applied between both electrode of a capacitor so as to polarize a ferroelectric layer sandwiched between the electrodes, and,...
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