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ASAP 2016: The 27th Annual IEEE International Conference on...
www.asap2016.org
Karthik Tanikella, Yohan Ko, Reiley Jeyapaul, Kyoungwoo Lee and Aviral Shrivastava. 11: :00, On-Chip Networks for Mixed-Criticality Systems Polydoros ...
Fei Hong - researchr alias
researchr.org
UnSync-CMP: Multicore CMP Architecture for Energy-Efficient Soft-Error ReliabilityReiley Jeyapaul, Fei Hong, Abhishek Rhisheekesan, Aviral Shrivastava, ...
CiteSeerX — Enabling Multithreading on CGRAs
citeseerx.ist.psu.edu
BibTeX @MISC{Shrivastava_enablingmultithreading, author = {Aviral Shrivastava and Reiley Jeyapaul and Mahdi Hamzeh and Sarma Vrudhula}, title = {Enabling ...
CiteSeerX — SPKM: A Novel Graph Drawing based Algorithm for...
citeseerx.ist.psu.edu
BibTeX. @MISC{Yoon_spkm:a, author = {Jonghee W. Yoon and Aviral Shrivastava and Sanghyun Park and Minwook Ahn and Reiley Jeyapaul and Yunheung ...
record conf/lctrts/ShrivastavaLJ10 - dblp
dblp.uni-trier.de
Aviral Shrivastava, Jongeun Lee, Reiley Jeyapaul: Cache vulnerability equations for protecting data in embedded processor caches from soft ...
Reiley Jeyapaul - DBLPdblp.org › Persons
dblp.org
Abhishek Rhisheekesan , Reiley Jeyapaul, Aviral Shrivastava : Control Flow Checking or Not? (for Soft Errors). ACM Trans. Embed. Comput. Syst.
Search results for "runtime scheduling" – FacetedDBLP
dblp.l3s.de
Aviral Shrivastava, Jared Pager, Reiley Jeyapaul, Mahdi Hamzeh, Sarma B. K. Vrudhula: Enabling Multithreading on CGRAs. ICPP : 2011: DBLP DOI BibTeX RDF:
Create a SciFeed alert for new publications - MDPIwww.mdpi.com › scifeed_display
www.mdpi.com
Reiley Jeyapaul. Jongho Kim. Youngbin Kim. Kyoungwoo Lee. Aviral Shrivastava. With settings. Email: Freq: Daily, Weekly, Monthly ...
Code Transformations for TLB Power Reduction | SpringerLink
link.springer.com
Reiley Jeyapaul Affiliated with Compiler and Microarchitecture Laboratory, Arizona State University Email author , Aviral Shrivastava Affiliated with Compiler and ...
System Reliability - Carole-Jean Wu - Google Sitessites.google.com › site › carolejeanwu › publications-by-topics › system-rel...
sites.google.com
Aviral Shrivastava, Abhishek Rhisheekesan, Reiley Jeyapaul, and Carole-Jean Wu. In Proceedings of the 51st Annual Design Automation Conference,
CML Enabling Multithreading on CGRAs Reiley Jeyapaul, Aviral ...slideplayer.com › slide
slideplayer.com
CML Enabling Multithreading on CGRAs Reiley Jeyapaul, Aviral Shrivastava 1, Jared Pager 1, Reiley Jeyapaul, 1 Mahdi Hamzeh 12, Sarma Vrudhula 2 Compiler.
Reiley Jeyapaul and Aviral Shrivastava Compiler-Microarchitecture ...
slideplayer.com
Presentation on theme: "Reiley Jeyapaul and Aviral Shrivastava Compiler-Microarchitecture Lab"— Presentation transcript: 1 B2P2: Bounds Based Procedure ...
Control flow checking or not? (for Soft Errors) — Arizona State...
asu.pure.elsevier.com
Abhishek Rhisheekesan, Reiley Jeyapaul, Aviral Shrivastava · IAFSE-CIDSE: Computer Science and Engineering · IAFSE-CIDSE: Embedded ...
NSF Award Search: Award # CAREER: Compiler Techniques for...
nsf.gov
Reiley Jeyapaul and Aviral Shrivastava.. "Enabling Energy Ef?cient Reliability in Embedded Systems Through Smart Cache Cleaning.," ...
Preliminary Program
www.scopesconf.org
B2P2: Bounds Based Procedure Placement for Instruction TLB Power Reduction in Embedded Systems. Reiley Jeyapaul and Aviral Shrivastava Compiler and ...
Code Transformations for TLB Power Reduction - ProQuestsearch.proquest.com › openview › 1.pdf
www.proquest.com
Reiley Jeyapaul · Aviral Shrivastava. Received: 30 June Accepted: 13 December Published online: 21 January
Code coding transformation - PowerPoint PPT Presentationfr.slideserve.com › search › code-coding-transformation-ppt-presentation
fr.slideserve.com
Reiley Jeyapaul, Sandeep Marathe, and Aviral Shrivastava Compiler Microarchitecture Laboratory Arizona State University. Translation Lookaside Buffer.
PPT - Quantitative Analysis of Control Flow Checking Mechanisms for...
www.slideserve.com
Quantitative Analysis of Control Flow Checking Mechanisms for Soft Errors. Aviral Shrivastava , Abhishek Rhisheekesan , Reiley Jeyapaul , and Carole-Jean...
Research Projects and Publication | Carole-Jean Wu
faculty.engineering.asu.edu
Aviral Shrivastava, Abhishek Rhisheekesan, Reiley Jeyapaul, and Carole-Jean Wu. In Proceedings of the 51st Annual Design Automation Conference (DAC),
International Journal of Parallel Programming
www.springerprofessional.de
| Issue Code Transformations for TLB Power Reduction. Reiley Jeyapaul, Aviral Shrivastava | Issue H-NMRU: An ...
Systematic Methodology for the Quantitative Analysis of...
asu.pure.elsevier.com
Systematic Methodology for the Quantitative Analysis of Pipeline-Register Reliability. Reiley Jeyapaul, Roberto Flores, Alfonso Avila, Aviral Shrivastava.
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