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Prateep Tuntasood, 60, Cincinnati, US, Scioto St
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Prateep Tuntasood, 60, Mountain View, US, Fayette Dr, Apt 509
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Prateep Tuntasood, 60, San Jose, US, Centerwood Way
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Prateep Tuntasood, 60, San Jose, US, Silverwood Creek Ct
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Interests
Prateep Tuntasood - Patents
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Prateep Tuntasood patents Recent bibliographic sampling of Prateep Tuntasood patents listed/published in the public domain by the USPTO (USPTO Patent Application
Ben Sheen - Patents
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Ben Sheen patents Recent bibliographic ... Geeng-chuan Michael Chern, Ben Sheen, Jonathan Pabustan, Prateep Tuntasood, Der-tsyr Fan, Yaw Wen Hu Silicon ...
Yaw Wen Hu - Patents
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Inventors: Yaw Wen Hu, Prateep Tuntasood (Silicon Storage Technology, Inc.) Method for erasing a flash memory cell or an array of ...
Business Profiles
patentbuddy: Prateep Tuntasood
SILICON STORAGE TECHNOLOGY, INC., San Jose, CA, US
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View Prateep Tuntasood's business profile as Manager at Integrated Silicon Solution Inc and see work history, affiliations and more.
Related Documents
Proceedings of the AFOSR Special Conference on Prime-Power for ...
www.dtic.mil
(b) Prateep Tuntasood, "Use of Activated Gold Donor in Silicon for. Fabrication of MOS and Photoconductive Infrared Detectors,". M.S. Thesis ...
Miscellaneous
Prateep Tuntasood | LinkedIn
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Prateep Tuntasoods berufliches Profil anzeigen LinkedIn ist das weltweit größte berufliche Netzwerk, das Fach- und Führungskräften wie Prateep Tuntasood ...
US A1 - Array Of Non-volatile Memory Cells
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An array of nonvolatile memory cells comprises a substantially single crystalline semiconductor substrate of a first conductivity type, having a planar...
US B2 - Flash memory cells with separated self-aligned select...
patents.google.com
Flash memory and process of fabrication in which vertically stacked pairs of floating gates and control gates are formed on opposite sides of a source...
US A1 - Process of Fabricating Flash Memory with Enhanced...
patents.google.com
Self-aligned split-gate flash memory cell array and process of fabrication in which erase and select gates are positioned on opposite sides of stacked...
FIN-FET Non-Volatile Memory Cell, And An Array And Method Of...
www.patentsencyclopedia.com
Inventors: Yaw Wen Hu (Cupertino, CA, US) Yaw Wen Hu (Cupertino, CA, US) Prateep Tuntasood (San Jose, CA, US) IPC8 Class: AH01L29788FI USPC Class:
US B1 - Method for fabricating tunnel window in EEPROM cell...
patents.google.com
A method for fabricating a tunnel window in an EEPROM cell that reduces or eliminates the initial active region overlap yet still compensates for tunnel...
EP A1 - A method of simultaneously fabricating bipolar and...
patents.google.com
A process is disclosed for simultaneously fabricating bipolar and complementary field effect transistors. The process includes the fabrication of buried layers...
EP A3 - A method of manufacturing a polysilicon emitter and a...
patents.google.com
Inventors, Michael P. Brassington, Reda R. Razouk, Monir H. El-Diwany, Prateep Tuntasood. Applicant, National Semiconductor Corporation. Export Citation ...
Sydex.net: People Search | Renee Neubert, Susan Stover, Brandon Arnett
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People search: find Photos, Location, Education, Job!
ClaimParse | Patent
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Inventorship, Nhan Do, Saratoga, CA (US) Hieu Van Tran, San Jose, CA (US) Chien-Sheng Su, Saratoga, CA (US) Prateep Tuntasood, San Jose, CA (US).
Method for Erasing a Flash Memory Cell or an Array of Such Cells...
www.patentsencyclopedia.com
Patent applications by Prateep Tuntasood, San Jose, CA US
US A1 - Semiconductor device and method of producing the...
patents.google.com
A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a...
Patent US Flash memory with enhanced program and erase...
patents.google.com
Self-aligned split-gate flash memory cell array and process of fabrication in which erase and select gates are positioned on opposite sides of stacked floating...
US A1 - NAND Flash Memory with Densely Packed Memory Gates...
patents.google.com
NAND flash memory cell array and fabrication process in which cells having memory gates and charge storage layers are densely packed, with the memory...
US A - Electrically erasable programmable read-only memory with...
www.google.com.do
An erasable programmable read-only memory with NAND cell structure is disclosed which has memory cells provided on a N type substrate. The memory cells...
Patent US Semiconductor device having inversion inducing...
patents.google.com
A semiconductor device is characterized by comprising a semiconductor substrate, a first insuring film formed on the semiconductor substrate, a plurality of...
US B1 - Memory device having A P+ gate and thin bottom oxide...
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US *, 26 Jul 2004, 26 Jan 2006, Prateep Tuntasood, NAND flash memory with densely packed memory gates and fabrication process.
US B2 - Method and apparatus for reducing operation disturbance...
patents.google.com
A memory array has a plurality of memory cells, arranged in a plurality of rows and columns. Each cell has at least four terminals. The array has a...
WO A1 - Non-volatile memory cells with enhanced channel...
patents.google.com
Wynalazcy, Nhan Do, Hieu Van Tran, Chien Sheng SU, Prateep Tuntasood. Wnioskodawca, Silicon Storage Technology, Inc. Eksportuj cytowanie, BiBTeX ...
US B2 - Bidirectional split gate NAND flash memory structure...
patents.google.com
A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region...
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