Networks-on-Chips: Theory and Practice - Google Books
books.google.cz
Michihiro Koibuchi and Hiroki Matsutani CONTENTS 3.1 Introduction 3.2 Switch-to-Switch Flow Control Switching Techniques Store-and-Forward ...
MULTICORE SYSTEMS ON-CHIP - Ben Abadallah Abderazek - Google Books
books.google.de
701–715, Jul, Hiroki Matsutani, Michihiro Koibuchi, and Hideharu Amano, Enforcing Dimension-Order Routing in On-Chip Torus Networks without Virtual ...
Parallel and Distributed Processing and Applications: 4th...
books.google.de
... in the design Enforcing Dimension-Order Routing in On-Chip Torus Networks Without Virtual Channels Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano.
Nature-Inspired Networking: Theory and Applications - Google Books
books.google.by
559–564. ACM, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, and Timothy Mark Pinkston. A lightweight fault-tolerant mechanism for network-onchip. In Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip, pp. 13–22. IEEE Computer Society, Yana E Krasteva, Eduardo ...
CiteSeerX — Layout-conscious Random Topologies for HPC Off-chip...
citeseerx.ist.psu.edu
@MISC{Koibuchi_layout-consciousrandom, author = {Michihiro Koibuchi and Ikki Fujiwara and Hiroki Matsutani and Henri Casanova}, title = {Layout-conscious ...
1 Michihiro Koibuchi, Takafumi Watanabe, Atsushi Minamihata, Masahiro...
pdfslide.net
* Michihiro Koibuchi, Takafumi Watanabe, Atsushi Minamihata, Masahiro Nakao, Tomoyuki Hiroyasu, Hiroki Matsutani, and Hideharu Amano .jp...
A Variable-pipeline On-chip Router Optimized to Traffic Pattern
nocarc.diit.unict.it
Router Optimized to Traffic. Pattern. Yuto Hirata (Keio University). Hiroki Matsutani (University of Tokyo). Michihiro Koibuchi (National Institute of Informatics).
Michihiro Koibuchi*, Hiroki Matsutani** Hideharu Amano**. Timothy...
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Michihiro Koibuchi*, Hiroki Matsutani** Hideharu Amano**. Timothy Mark Pinkston*** *National Institute of Informatics, Japan/JST, Japan *Keio University, Japan...
A Routing Strategy for Inductive-Coupling Based Wireless 3-D NoCs by...
link.springer.com
A Routing Strategy for Inductive-Coupling Based Wireless 3-D NoCs by Maximizing Topological Regularity. Authors; Authors and affiliations. Daisuke Sasaki; Hao Zhang; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano. Daisuke Sasaki. 1. Hao Zhang. 1. Hiroki Matsutani. 1. Michihiro Koibuchi. 2. Hideharu Amano. 1.
All web results to the name "Michihiro Koibuchi"
Publications (since 2013) - Blackbus Research Group
sites.google.com
Blackbus Research Group. Search this site Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, "A Configurable Switch Mechanism for Random NoCs", ...
Jose Miguel - Google Scholar Citations
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Jose Duato,; Jose Flich,; Olav Lysne,; Hiroki Matsutani,; Hideharu Amano,; Michihiro Koibuchi,; José-V. Benlloch-Dualde,; Jose Luis Poza Luján,; Juan-Luis ...
A Multi-Vdd Dynamic Variable-Pipeline On-Chip Router for CMPs - ppt...
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A Multi-Vdd Dynamic Variable-Pipeline On-Chip Router for CMPs Hiroki Matsutani Yuto Hirata Michihiro Koibuchi Kimiyoshi Usami Hiroshi Nakamura Hideharu.
Jose Miguel Montanana (NII, Japan) Michihiro Koibuchi (NII, Japan
vdocuments.site
Jose Miguel Montanana (NII, Japan) Michihiro Koibuchi (NII, Japan） Hiroki Matsutani （U of Tokyo, Japan） Hideharu Amano（Keio U/ NII, Japan） Stabilizing Path Modification of Power-Aware On/Off Interconnection Networks; HPC networks (Infiniband, GbE) On/Off link activation method Reducing power consumption of ...
PPT – Michihiro Koibuchi, Hiroki Matsutani PowerPoint presentation |...
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PPT – Michihiro Koibuchi, Hiroki Matsutani PowerPoint presentation | free to view - id: 1b71cc-ZDc1Z. Loading. The Adobe Flash plugin is needed to view this ...
KOIBUCHI Michihiro - 国立情報学研究所/National Institute of Informatics
www.nii.ac.jp
Nguyen T. Truong, Ikki Fujiwara, Michihiro Koibuchi, Khanh-Van Nguyen ... Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao ...
A lightweight fault-tolerant mechanism for network-on-chip —...
keio.pure.elsevier.com
A lightweight fault-tolerant mechanism for network-on-chip. Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, Timothy Mark Pinkston. Department of ...
…e Big Data (EBD): Next Generation Big Data Infrastructure...
superfri.org
Supercom…ng frontiers and innovations Journal Content Search ... Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, D. Frank Hsu, and Henri Casanova.
NSF Award Search: Award # Investigation of...
www.nsf.gov
Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, and Timothy Mark Pinkston. "A Lightweight Fault-Tolerant Mechanism for Network-on-Chip," Proceedings ...
18th Asia and South Pacific Design Automation Conference (ASP-DAC...
www.aspdac.com
Best Paper Award. 1B-1: A Case for Wireless 3D NoCs for CMPs. Hiroki Matsutani (Keio Univ., Japan), Paul Bogdan, Radu Marculescu (Carnegie Mellon Univ., U.S.A.), Yasuhiro Take, Daisuke Sasaki, Hao Zhang (Keio Univ., Japan), Michihiro Koibuchi (NII, Japan), Tadahiro Kuroda, Hideharu Amano (Keio ...
Session 15: Interconnection Networks
www.cecs.uci.edu
Hiroki Matsutani, Michihiro Koibuchi and Hideharu Amano. Table-lookup based Crossbar Arbitration for Minimal-Routed, 2D Mesh and Torus Networks
SLD
research.ece.cmu.edu
... Hiroki Matsutani, Paul Bogdan, Radu Marculescu, Yasuhiro Take, Daisuke Sasaki, Hao Zhang, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano photo.
IEICE Technical Report, vol 115, no 174, 2015
ken.ieice.org
Random memory network design for Hybrid Memory Cubes Daichi Fujiki, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.)
Publications - Computer Engineering
cps.usc.edu
Zhiliang Qian, Da-Cheng Juan, Paul Bogdan, Chi-Ying Tsui, Diana Marculescu and Radu Marculescu, A comprehensive and accurate latency model for Network-on-Chip performance analysis, ASP-DACHiroki Matsutani, Michihiro Koibuchi, Ikki Fujiwara, Takahiro Kagami, Yasuhiro Take, Tadahiro Kuroda, ...
Skywalk: A topology for HPC networks with low-delay switches —...
keio.pure.elsevier.com
Skywalk: A topology for HPC networks with low-delay switches. Ikki Fujiwara, Michihiro Koibuchi, Hiroki Matsutani, Henri Casanova. Keio University Hospital. Research output: Chapter in Book/Report/Conference proceeding › Conference contribution. 11 Citations ...
Run-time power-gating techniques for low-power on-chip networks...
keio.pure.elsevier.com
Run-time power-gating techniques for low-power on-chip networks. Hiroki Matsutani ; Michihiro Koibuchi ; Hiroshi Nakamura ; Hideharu Amano.
best_papers [CANDAR'16]
is-candar.org
CANDAR Best Paper. Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Koibuchi and Hideharu, LOREN: A Scalable Routing Method for Layout-Conscious Random Topologies ...
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