Kumara Ratnayake and Aishy Amer - Free people check

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CiteSeerX — AN FPGA-BASED IMPLEMENTATION OF SPATIO-TEMPORAL OBJECT...

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@MISC{Ratnayake_anfpga-based, author = {Kumara Ratnayake and Aishy Amer}, title = {AN FPGA-BASED IMPLEMENTATION OF SPATIO-TEMPORAL OBJECT …

Kumara Ratnayake - dblpdblp.org › Persons

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Kumara Ratnayake, Aishy Amer: Embedded architecture for noise-adaptive video object detection using parameter-compressed background ...

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"Kumara Ratnayake" ... Kumara Ratnayake, Aishy Amer · CISSFetch | Report | Google · A real-time implementation of chaotic contour tracing ...

An FPGA Architecture of Stable-Sorting on a Large Data Volumewww.semanticscholar.org › paper › An-FPGA-Architectur...

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Kumara Ratnayake, Aishy Amer; Published in 41st Annual Conference on… 2007; Computer Science. This paper proposes a single-chip scalable and compact ...

Embedded architecture for noise-adaptive video object ...www.infona.pl › resource › bwmeta1.element.springer-...

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Embedded architecture for noise-adaptive video object detection using parameter-compressed background modeling. Kumara Ratnayake, Aishy Amer.

An FPGA-Based Implementation of Spatio-Temporal Object Segmentation |...

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... hardware platform which consists of a frame grabber with a user programmable FPGA - Xilinx Virtex-II Pro. Kumara Ratnayake, Aishy Amer.

ICIP 2006, Atlanta, GA, USA

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WP-P7.1: H.264-BASED MULTIPLE DESCRIPTION VIDEO CODER AND ITS DSP IMPLEMENTATION ... Kumara Ratnayake; Concordia University. Aishy Amer; Concordia ...

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Kumara Ratnayake, Aishy Amer. Benchmarking and hardware implementation of ...

ICIP 2006, Atlanta, GA, USA

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11 Oct Kumara Ratnayake; Concordia University. Aishy Amer; Concordia University. WP-P7. 5: A MEMORY-SAVING SYSTEM INCLUDING DWT AND EC FOR JPEG

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Kumara Ratnayake and Aishy Amer Free People Check