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Low Power VLSI, Hendrawan Soeleman, Sun Microsystems, Kaushik Roy, Purdue Univeristy Clock Powered CMOS, Nestoras Tzartzanis, ISI › plp
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Low Power VLSI, Hendrawan Soeleman, Sun Microsystems, Kaushik Roy, Purdue Univeristy Clock Powered CMOS, Nestoras Tzartzanis, ISI › Computer-Engineer...
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Digital CMOS logic operation in the sub-threshold region. In GLSVLSI : Hendrawan Soeleman, Kaushik Roy, Bipul Paul Robust ultra-low ...
Low Power VLSI Design: Fundamentalsbooks.google.com › books
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Hendrawan Soeleman, Kaushik Roy and Bipul C. Paul, “Robust subthreshold logic for ultralow power operation.” IEEE Transactions on Very Large Scale ...
14th International Conference on VLSI Design Researchr
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[doi] · Sub-Domino Logic: Ultra-Low Power Dynamic Sub-Threshold Digital LogicHendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul. › publication › vlsid:2001
IDD Waveforms Analysis for Testing of Domino and Low ...
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by H Soeleman · · Cited by 5 — Hendrawan Soeleman. Dinesh Somasekhar. Kaushik Roy. School of Electrical and Computer Engineering. Purdue University, West Lafayette, IN , USA. › glsvlsid
Novel Ultra Low Power-Delay-Product Full Adder Cells in ...
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May 1, — [6] Hendrawan Soeleman, Kaushik Roy, “Digital. CMOS logic operation in the sub-threshold region,” in. Proc. Great Lakes Symp. VLSI, pp. › handle › IJCNT
Reliable Chip Design from Low Powered Unreliable CORA
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by SK Grandhi · — [128] Hendrawan Soeleman, Kaushik Roy, and Bipul C Paul. Robust subthreshold logic for ultra-low power operation. Very Large Scale Integration (VLSI) ... › bitstream › handle › satish_ph...
BibTeX records: Kaushik Roy DBLP
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@article{DBLP:journals/tvlsi/KimSR03, author = {Chris Hyung{-}Il Kim and Hendrawan Soeleman and Kaushik Roy}, title = {Ultra-low-power {DLMS} adaptive ... › Persons › Kaushik Roy 0001
Dynamic Threshold MOSFET for Low Power VLSI Circuit Design
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[12] Hendrawan Soeleman, Kaushik Roy & Bipul C. Paul; “Robust Sub-Threshold Logic for Ultra-Low Power Operation” IEEE Transactions on VLSI systems, VOL.9, ... › ijet › article › view
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Bibliographic content of ACM Great Lakes Symposium on VLSI 2000
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Electronic Edition (link) BibTeX · Hendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul: Robust subthreshold logic for ultra-low power operation
The computer engineering handbook (eBook, 2004) [WorldCat.org]www.worldcat.org › title › computer-engineering-handbook › oclc
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... CSEMImplementation-Level Impact on Low Power Design,Katsunori Seno, SONYLow Power VLSI, Hendrawan Soeleman, Sun Microsystems, Kaushik Roy, ...
Novel Ultra Low Power-Delay-Product Full Adder Cells in 45nm Fin ...www.thefreelibrary.com › ... › May 1, 2014
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[6] Hendrawan Soeleman, Kaushik Roy, "Digital CMOS logic operation in the sub-threshold region," in Proc. Great Lakes Symp. VLSI, pp , Mar
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Subthreshold circuits: Design, implementation and application
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by H Kanitkar · · Cited by 11 — [49] Hendrawan Soeleman, Kaushik Roy, and Bipul C. Paul. Robust subthreshold logic for ultra-low power operation. IEEE Transactions on VLSI ... › cgi › viewcontent
مقاله New Dynamic Body Biasing NMOS Network Technique ...
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Hendrawan Soeleman, Kaushik Roy, and Bipul Paul" Sub-Domino Logic: Ultra-Low ... Y. Taur and T. H. Ning, Fundamentas of Modern VLSI . › doc
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Hendrawan Soeleman, Kaushik Roy. ACM Great Lakes Symposium on VLSIFetch | Report ...
SIGDA, Super Compendium, GLSVLSI 2000, Table of Contents
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Invited Paper: Low Power and High Performance Design Challenges in Future Technologies ... Hendrawan Soeleman, Kaushik Roy Low Power High Speed Analog-to ...
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