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Guest Talk: Sterpone & Bernadeschi | CITEC
www.cit-ec.de
Luca Sterpone: Title: Fault Tolerance Design Techniques for SRAM-based FPGAs inSafety-Critical ApplicationsAbstract:
Ingegnere a un soffio dal titolo europeo - Il Tirreno Pisa
www.iltirreno.it
Ha vinto la semifinale del premio organizzato sulle tesi di dottorato
7th-ICSCC 2022: Chongqing, China
www.icscc.org
Welcome Assoc. Prof. Cinzia Bernardeschi, University of Pisa, Italy to join in our conference committees Welcome Prof. Chin-Chen Chang ...
Telephone & Addresses
Formal Verification and Co-Simulation in the Design of a Synchronous...
ideas.repec.org
Downloadable! Mechatronic systems are a class of cyber-physical systems, whose increasing complexity makes their validation and verification more and more...
Network Profiles
LinkedIn: Cinzia Bernardeschi - Associate Professor - Università di Pisa | LinkedIn
Visualizza il profilo di Cinzia Bernardeschi su LinkedIn, la più grande comunità professionale al mondo. Cinzia ha indicato 2 esperienze lavorative sul suo ...
Cinzia Bernardeschi | BibSonomy
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DBLife: Giuseppe Lettieri
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Cinzia Bernardeschi, Nicoletta De Francesco, Giuseppe Lettieri, Luca Martini. Softw., Pract. Exper. (34): (2004). Web Search BibTeX Download: 17:
Business Profiles
Researchgate: Cinzia Bernardeschi
Pisa, PI, Italy
Education
IEICE Trans - Using Process Algebras for the Semantic Analysis of...
search.ieice.org
Cinzia BERNARDESCHI · Andrea BONDAVALLI · Luca SIMONCINI Publication IEICE TRANSACTIONS on Information and Systems Vol.E78-D ...
Projects
HOL theorem-proving system / [Hol-info] Second Call for Papers: FMICS...
sourceforge.net
... Spain) Jiri Barnat (Masaryk University, Czech Republic) Cinzia Bernardeschi (University of Pisa, Italy) Simona Bernardi (Centro Universitario ...
Books & Literature
Cinzia Bernardeschi | XanEdu Customization Platform
www.academicpub.com
Author: Cinzia Bernardeschi. Results. A Formal Verification Environment for Railway Signaling System Design Springer Science+Business Media
A Formal Veri cation Environment for Railway Signaling System Cnrpuma.isti.cnr.it/download.php?DocFile=1995-TR-004_.ps...it...
puma.isti.cnr.it
CINZIA BERNARDESCHI. .it. Dipartimento di Ingegneria della Informazione, Universit a di Pisa, Italy. ALESSANDRO FANTECHI.
Author 214 home page
www.cse.dmu.ac.uk
Author 214 home page. Raw Data File. Using Standard Verifier to Check Secure Information Flow in Java Bytecode: Cinzia Bernardeschi: Edit Page: Nicoletta ...
Introduzione al linguaggio di specifica LOTOS - Cinzia Bernardeschi -...
books.google.de
Introduzione al linguaggio di specifica LOTOS. Front Cover. Cinzia Bernardeschi. Servizio editoriale universitario, pages. 0 Reviews ...
Related Documents
EPTCS 310: Formal Integrated Development Environment
arxiv.org
Cinzia Bernardeschi (University of Pisa); José Creissac Campos (University of Minho); Paul Curzon (Queen Mary University of London) ...
CiteSeerX — A Formal Verification Environment for Railway Signaling...
citeseerx.ist.psu.edu
by C Bernardeschi · · Cited by 82 — by Cinzia Bernardeschi , Alessandro Fantechi , Stefania Gnesi , Salvatore Larosa , Giorgio Mongardi , Dario Romano. Venue: Formal Methods in System Design. › viewdoc › summary
cinzia bernardeschi - Academia.eduindependent.academia.edu › cinziabernardeschi
independent.academia.edu
cinzia bernardeschi studies Internet Routing Protocol, Routing Protocols in WSN, and IEEE WLAN.
Cinzia Bernardeshi - ETAPS 2019
conf.researchr.org
Cinzia Bernardeschi received the Laurea degree in Computer Science in and the PhD degree in 1996, both from the University of Pisa, Pisa, Italy. › profile › cinziabernardeshi
Scientific Publications
UA2TPG: An untestability analyzer and test pattern generator ...www.sciencedirect.com › science › article › abs › pii
www.sciencedirect.com
Cinzia Bernardeschi received the Laurea degree in computer science in and the Ph.D. degree in 1996, both from the University of Pisa, Pisa, Italy.
dblp: Cinzia Bernardeschi
dblp.uni-trier.de
Cinzia Bernardeschi, Paolo Masci, Davide Caramella, Ruggero Dell'Osso: The benefits of using interactive device simulations as training material for clinicians: an experience report with a …
dblp: The Computer Journal, Volume 47, 2004
dblp.uni-trier.de
Bibliographic content of The Computer Journal, Volume 47, 2004
BMP08 - Universität Ulm
www.uni-ulm.de
@inproceedings{BMP08, author = {Cinzia Bernardeschi and Paolo Masci and Holger Pfeifer}, title = {Early Prototyping of Wireless Sensor Network
Publications
Formal Verification and Co-Simulation in the Design of MDPI
www.mdpi.com
by C Bernardeschi · · Cited by 6 — Formal Verification and Co-Simulation in the Design of a Synchronous Motor Control Algorithm. by. Cinzia Bernardeschi. › ...
Journal of Computer Virology and Hacking Techniques | Editors
www.springer.com
Editorial Board Dharma P AGRAWAL, University of Cincinnati, USA Johann BARBIER, ARX Arcéo, Rennes, France Chaouki BEKRAR, VUPEN, Annapolis, USA Sofia BEKRAR, VUPEN, Annapolis, USA Cinzia BERNARDESCHI, University of Pisa, Italy Guillaume BONFANTE, Université de Lorraine, LORIA, Nancy, France Jean-Marie BORELLO, DGA-MI, Bruz, France Silvio ...
JACK goes Industrial - ERCIM
www.ercim.eu
Apr 25, — JACK goes Industrial. by Cinzia Bernardeschi, Alessandro Fantechi and Stefania Gnesi. JACK, Just Another Concurrency Kit, is an environment ... › Ercim_News › enw25 › gnesi
A Formal Verification Environment for Railway Signaling System Design...
link.springer.com
A fundamental problem in the design and development of embedded control systems is the verification of safety requirements. Formal methods, offering a math
Miscellaneous
cinzia bernardeschi - Google Scholar Citations
scholar.google.co.uk
This "Cited by" count includes citations to the following articles in Scholar. The ones marked * may be different from the article in the profile.
cinzia bernardeschi - Google Scholar Citationsscholar.google.ca › citations
scholar.google.ca
C Bernardeschi, A Fantechi, S Gnesi, S Larosa, G Mongardi, D Romano. Formal Methods in System Design 12 (2), Model checking ...
CoSim-CPS-18
sites.google.com
Cinzia Bernardeschi, University of Pisa, Italy, cinzia (dot) bernardeschi (at) iet (dot) unipi (dot) it; Paolo Masci, INESC TEC and Universidade do Minho, Portugal, ...
Cinzia Bernardeschi - Prof. Università di Pisa (UNIPI) | Docsity
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Scopri tutti i documenti disponibili per Cinzia Bernardeschi o caricane uno tu su Docsity e guadagna punti download.
TEACUP - Members - Google Sites
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Gianluca Dini · Cinzia Bernardeschi · Giuseppe Lettieri · Pericle Perazzo · Giovanni Nardini · Michele La Manna · Mariano Basile ... › unipi.it › teacup › members
CiteSeerX — Citation Query Cinzia Bernardeschi, and Nicoletta De...
citeseer.uark.edu
CiteSeerX - Scientific documents that cite the following paper: Cinzia Bernardeschi, and Nicoletta De Francesco. Java bytecode verification for secure...
Dr. Cinzia Bernardeschi - Mosharaka for Research and Studiesmosharaka.net › ...
mosharaka.net
Name, Dr. Cinzia Bernardeschi. Affiliation, University of Pisa, Pisa, Italy. Topics, FPGA Design and Implementation Algorithms and Applications on FPGAs.
Home Page of Cinzia Bernardeschi | BibSonomywww.bibsonomy.org › url
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Home Page of Cinzia Bernardeschi. homepages , Cinzia Bernardeschi, Home Page, https://orcid.org , University of Pisa, Italy ...
TDGS - "Cinzia Bernardeschi"
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An inter-processor communication interface for data-flow centric heterogeneous embedded multiprocessor systems
BERNARDESCHI, CINZIA
arpi.unipi.it
CINECA IRIS Institutional Research Information System. IRIS è la soluzione IT che facilita la raccolta e la gestione dei dati relativi alle attività e ai prodotti della ricerca. Fornisce a ricercatori, amministratori e valutatori gli strumenti per monitorare i risultati della ricerca, aumentarne la visibilità e allocare in modo efficace le risorse disponibili.
A tool for checking secure interaction in Java Cards - Archive ...
hal.archives-ouvertes.fr
Marco Avvenuti, Cinzia Bernardeschi, Nicoletta de Francesco, Paolo Masci. A tool for checking secure interaction in Java Cards. 12th European Workshop on ... › hal-...
A Petri nets semantics for data flow networks
www.infona.pl
Abstract. This work presents a truly concurrent operational semantics for nondeterministic data flow networks. We introduce a model, the df-process, which is a...
ICISSP ForSE
icissp.scitevents.org
Cinzia Bernardeschi, University of Pisa, Italy Rosangela Casolare, University of Molise, Italy Umberto Di Giacomo, University of Molise, Italy › ForSE
A Formal Verification Environment for Railway Signaling System Design...
www.sciweavers.org
A Formal Verification Environment for Railway Signaling System Design
Medical Cyber Physical Systems Workshop 2018
rtg.cis.upenn.edu
Cinzia Bernardeschi, Paolo Masci, Davide Caramella and Ruggero Dell'Osso. 12:30-14:00, Lunch Break. 14:00-14:30 14:30-15:00 › mcps-workshop-2018
Early Prototyping of Wireless Sensor Network Algorithms in PVS |...
www.springerprofessional.de
We describe an approach of using the evaluation mechanism of the specification and verification system PVS to support formal design exploration of
Publication Details - SciTePress
www.scitepress.org
Authors: Cinzia Bernardeschi 1 ; Marco Di Natale 2 ; Gianluca Dini 1 and Maurizio Palmieri 1. Affiliations: 1 University of Pisa, Italy ; 2 Scuola Superiore ... › Link
Special issue of "Formal Methods in System Design"
fmics.inria.fr
Special issue of "Formal Methods in System Design" ... Cinzia Bernardeschi, Alessandro Fantechi, Stefania Gnesi, Salvatore Larosa, Giorgio Mongardi, Dario Romano
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