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Chin-I Liao - Patents
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Chin-I Liao patents. Recent bibliographic sampling of Chin-I Liao patents listed/ published in the public domain by the USPTO (USPTO Patent Application #,Title) ...
Business Profiles
patentbuddy: Chin-I Liao
UNITED MICROELECTRONICS CORP., Tai-Nan City, TW, US
patentbuddy: Chin I Liao
UNITED MICROELECTRONICS CORP., Tai-Nan, TW, US
Books & Literature
SiGe and Ge: Materials, Processing, and Devices - Google Books
books.google.de
The second International SiGe & Ge: Materials, Processing, and Devices Symposium was part of the ECS conference held in Cancun, Mexico from October 29-Nov...
Related Documents
High Quality SiGe:B of High Ge Layer for 14nm and Beyond FINFET...
ecst.ecsdl.org
High Quality SiGe:B of High Ge Layer for 14nm and Beyond FINFET Processes. Chin I Liao,; Chun Yua Chen,; Stan Yu,; Chin Cheng Chien, ...
NMOS SiP Epitaxy Process - Optimizing Facet Growth
ecst.ecsdl.org
Chin I Liao,; Chin Cheng Chien,; Michael Chan,; Chan Lon Yang,; JY Wu,; Chuck Chung,; and Balasubramanian Ramachandran. NMOS SiP Epitaxy Process ...
Scientific Publications
Composite Structures | Vol 65, Issue 2, Pages (August 2004) |...
www.sciencedirect.com
Compressive strength of reinforced concrete column confined by composite material. Original Research Article; Pages ; Huei-Jeng Lin, Chin-I Liao.
Video & Audio
SamLiao's Play List - YouTube
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"SamLiao's Play List", a playlist created by Chin-I Liao SamLiao's Play List. by Chin-I Liao. Alert icon. This playlist has no videos.
Miscellaneous
Chin-I Liao - Manager - UBP TransGlobe Securities ...
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View Chin-I Liao’s profile on LinkedIn, the world's largest professional community. Chin-I has 8 jobs listed on their profile. See the complete profile on LinkedIn and discover Chin-I’S ...
US A1 - Method for fabricating semiconductor device, and...
patents.google.com
Apr , Chin-I Liao, Semiconductor structure and method for making the same . US *, 19. Jan , 19. Juli 2012, Taiwan Semiconductor ...
US B2 - Semiconductor device having epitaxial layer
patents.google.com
Inventeurs, Chin-I Liao, Teng-Chun Hsuan, Chin-Cheng Chien. Cessionnaire d'origine, United Microelectronics Corp. Exporter la citation, BiBTeX, EndNote, ...
US B2 - Semiconductor device having metal gate and...
patents.google.com
A method of manufacturing a semiconductor device having metal gate includes providing a substrate having at least a dummy gate, a sacrificial layer...
Highly Selective Etching of GaAs on Al0.2Ga0.8As Using Citric...
esl.ecsdl.org
Chin-I. Liao, Mau-Phon Houng and Yeong-Her Wang z; Department of Electrical Engineering, Institute of Microelectronics, National ...
Chin-I Liao, Tainan City TW - Patent applications
www.patentsencyclopedia.com
Patent application number Description Published; : METHOD OF FORMING SELECTIVE AREA COMPOUND SEMICONDUCTOR EPITAXIAL LAYER - A method of forming a
Chin-I - Patent applications
www.patentsencyclopedia.com
Patent applications by Chin-I Liao, Tai-Nan City TW. Chin-I Liao, Tainan TW. Patent application number, Description, Published , COMPOUND ...
US B2 - Boat propeller with adjustable blades for adjusting the...
patents.google.com
A boat propeller comprises a hub formed of a first cylindrical member and a second cylindrical member detachably joined together. The second cylindrical...
US A1 - Method for forming silicon-germanium epitaxial...
patents.google.com
A method for forming a SiGe epitaxial layer is described. A first SEG process is performed under a first condition, consuming about 1% to 20% of the...
US A1 - Self-Aligned Fin Transistor Formed on a Bulk...
patents.google.com
Non-planar transistors, such as FinFETs, may be formed in a bulk configuration in the context of a replacement gate approach, wherein the semiconductor...
Inspection of defects and metallic contamination in SiGe:B CMOS using...
www.spiedigitallibrary.org
SPIE Digital Library Proceedings
Effective Surface Treatments for Selective Epitaxial SiGe Growth in...
www.infona.pl
Cyclical wet clean in DI-O<sub>3</sub>/SC1/DHF and low temperature bake in HCl/H<sub>2</sub> are presented as effective surface...
Effectiveness of Si Seed for Selective SiGe Epitaxial Deposition in...
ecst.ecsdl.org
Po Lun Cheng,; Chin I Liao,; Hou Ren Wu,; Yi Cheng Chen,; Chin Cheng Chien,; Chan Lon Yang,; S F Tzou,; Jinsong Tang,; Yonah Cho,; Errol Sanchez, ...
US A1 - Finfet transistor structure and method for making...
patents.google.com
A FINFET transistor structure includes a substrate, a fin structure, an insulating layer and a gate structure. The fin structure is disposed on the...
US A1 - Semiconductor structure and process thereof...
patents.google.com
A semiconductor structure includes agate structure, an epitaxial layer and a carbon-containing silicon germanium cap layer. The gate structure is located...
US A - Electric fan Google Patents
patents.google.com
The present invention relates an electric fan. The fan has a body and a fan assembly housed in the body. The fan is able to pivot and elevate/descend...
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ecst.ecsdl.org
High Quality SiGe:B of high Ge Layer for 14nm and Beyond FINFET Processes. *Chin I Liao a. , Chun Yua Chen a. , Stan Yu a. , Chin Cheng Chien a.
Effective of Si Seed for Selective SiGe Epitaxial Meeting Abstracts
ma.ecsdl.org
Po-Lun Cheng, Chin-I Liao, Hou Ren Wu, Yi-Cheng. Chen, Chin-Cheng Chien,. Chan-Lon Yang, and S F Tzou. United Microelectronics Corp., No 18, Nanke ...
US B2 - Method for forming void-free dielectric layer...
patents.google.com
A method for forming a dielectric layer free of voids is disclosed. First, a substrate, a first stressed layer including a recess, a second stressed...
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