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WhitePages: Chandrasekharan Kothandaraman | Whitepages
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WhitePages: Chandrasekar Kothandaraman | 5 records found | Whitepages
Chandrasekharan Kothandaraman. New York NY (Midtown Manhattan). Family. Soultana Nolan. Anna Nolan. Chris James Nolan. Age ––; Lives in New York ...
WhitePages: Chandrasekharn Kothandaraman | 5 records found | Whitepages
Chandrasekharan Kothandaraman. New York NY. Family. Soultana Nolan. Anna Nolan. Chris James Nolan. Age ––; Lives in New York NY; Related to Soultana ...
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Chandrasekharan KOTHANDARAMAN | Researcher
www.researchgate.net
Chandrasekharan Kothandaraman X. Chen D. Moy Subramanian Iyer We explore the use of oxygen vacancies for nonvolatile data storage by trapping electrons in the high-k, gate dielectric layer of...
patentbuddy: Chandrasekharan Kothandaraman
INTERNATIONAL BUSINESS MACHINES CORPORATION, Hopewell Junction, NY, US
Books & Literature
Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm...
doaj.org
Chandrasekharan Kothandaraman (IBM Corporation Systems and Technology Group, Hopewell Junction, NY , USA) Ben Himmel (Formerly with IBM ...
3D Integration in VLSI Circuits: Implementation Technologies and...
books.google.nl
Myongseob Kim Xilinx, Inc. San Jose, California Chandrasekharan Kothandaraman IBM T.J. Watson Research Center Yorktown Heights, New York M. Koyanagi ...
Related Documents
EFUSE SENSE CIRCUIT - International Business Machines Corporation
www.freepatentsonline.com
An eFuse reference cell on a chip provides a reference voltage that is greater than a maximum voltage produced by an eFuse cell having an unblown eFuse on the...
Scientific Publications
dblp: Chandrasekharan Kothandaraman
dblp.dagstuhl.de
List of computer science publications by Chandrasekharan Kothandaraman
Publications
SciFeed - MDPIwww.mdpi.com › scifeed_display
www.mdpi.com
By following authors. Pooja Batra. Spyridon Skordas. Douglas LaTulipe. Kevin Winstel. Chandrasekharan Kothandaraman. Ben Himmel. Gary Maier. Bishan He.
Miscellaneous
Nanoscale Magnetic Tunnel Junction Arrays For Sub-micrometer ...
uspto.report
The applicant listed for this patent is International Business Machines Corporation. Invention is credited to Eric Raymond Evarts, Pouya Hashemi, Chandrasekharan Kothandaraman, Virat Vasav Mehta, Alexander Reznicek.
Nathan Marchack - Patents and Patent Applications
researcher.draco.res.ibm.com
Nathan P Marchack, Bruce B Doris, Chandrasekharan Kothandaraman US Patent 10,727,398 Tapered VA structure for increased alignment tolerance and reduced sputter redeposition in MTJ devices
US A1 - Radio frequency-enabled electromigration fuse...
patents.google.com
Inventeurs, Subramanian S. Iyer, Chandrasekharan Kothandaraman, Gerard M. Salem. Cessionnaire d'origine, International Business Machines Corporation.
DE D1 - A semiconductor device having a control wiring layer...
patents.google.com
US A1 * Chandrasekharan Kothandaraman Optically and electrically programmable silicided polysilicon fuse device.
US A1 - Using electrically programmable fuses to hide...
patents.google.com
Inventor Anthony Bonaccio Karl Erickson John Fifield Chandrasekharan Kothandaraman Phil Paone William Tonti Current Assignee (The listed assignees may be inaccurate.
US A1 - Electrical antifuse having a multi-thickness...
patents.google.com
An electrical antifuse comprising a field effect transistor includes a gate dielectric having two gate dielectric portions. Upon application of electric...
US A - Single transistor non-valatile electrically alterable...
patents.google.com
A single transistor electrically programmable and erasable memory cell is disclosed. The single transistor has a source, a drain with a channel region...
US B2 - System for programming fuse structure by...
patents.google.com
The present invention provides a system, apparatus and method of programming via electromigration. A semiconductor fuse which includes a cathode and an...
US B1 - Silicide agglomeration poly fuse device
patents.google.com
A fusible link device and a method of making same. The fusible link device comprising a poly layer having a center undoped portion and two doped end...
US B1 - Compact single-poly two transistor EEPROM cell...
patents.google.com
A non-volatile memory cell at least partially formed in a semiconductor substrate. The cell comprises a first transistor comprising a high voltage NMOS...
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